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工艺整合工程师(PIE)
9千-1.6万·13薪
人 · 本科 · 5-7年工作经验 · 性别不限2025/01/02发布
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出口加工区科新路8号附6号

公司信息
达迩科技(成都)有限公司

外资(欧美)/1000-5000人

该公司所有职位
职位描述
Principle Duties and Responsibilities:
Wafer level bumping technology innovation and process implementation using internal and external production operations.
Coordinate wafer bumping developing project with customer, supplier, internal company business units and manufacturing sites to achieve goal.
Integrate product design, material, process flow, hardware alongside wafer level operations to achieve quality performance.
Oversee deployment new wafer level process and ramp WLP operations.
Work with product engineer and process engineer in resolving WLP production ramp issues.
Support production operations for continuous improvement alongside production sustaining team.
Expand WLP process technologies and capabilities for future product growth.
Knowledge, Skills and Abilities:
Requires a Master/Bachelor degree in Science / Engineering in major of Physics, Chemistry, Electronics or Material, >5 years of related experience in the areas of semiconductor manufacturing, product engineering, semiconductor packaging, research & develop or project management.
Must be well-organized, self-directed, self-starter, highly motivated, proactive problem solver with the ability to get results without owning resources and possessing direct authority.
Must be willing to work with other individuals and teams to achieve corporate goals.
Experience in semiconductor production, in particular regarding WLP bumping or CSP packaging operations (Photo, Etch, PVD, Plating).
Skilled of project management, communication (in both Mandarin and English) and process developing toolings.
Familiar and experienced with process control and problem solving methodologies such as SPC, MSA, APQP, DOE, 8D, PDCA.
Must be willing to travel internationally.
Position location at Chengdu, China reporting to Diodes Headquarters, USA.

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