Develop and maintain Ethenet/Serdes/GBE verification of : 1. RTL and netlist simulation 2. Constrained-Random-Verification based environment 3. System level verification with SVA 4. Create Functional/Assertion Coverage and drive Coverage Closure
Experienced with below skillset is plus :
1. Familiar with IEEE 802.3 standard 2. Familiar with Ethernet Switch 3. Familiar with digital design (incl. timing closure) 4. Familiar with System Verilog or UVM testbench 5. Scripting languages such as C shell, Perl, Makefile