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Sr. DFT Engineer - J10863CD
30-50万/年
人 · 硕士 · 4年及以上工作经验 · 性别不限2024/11/12发布
五险一金补充医疗保险补充公积金员工旅游餐饮补贴绩效奖金股票期权弹性工作定期体检带薪假期

四川省成都市高新区AI 创新中心B6栋2单元4楼

公司信息
豪威科技(上海)有限公司

外资(欧美)/1000-5000人

该公司所有职位
职位描述
工作职责:
1. Define chip level DFT test spec and test structure.
2. Be responsible for DFT flow/methodology evolvement, DFT logic implementation and verification, including MBIST, Scan, Boundary Scan and IP test.
3. Be responsible for pattern generation along with pre-layout simulation/post-layout simulation of each DFT test item.
4. Be responsible for DFT SDC release and check, along with DFT related STA, power and IR task forces.
5. Co-work with production and testing team, complete ATE bring up/pattern tuning and yield improvement work of all DFT test items and drive low or even zero DPPM.
任职资格:
1. Major in EE or related. Master degree with 4~6 years’ experience in DFT-related areas.
2. Solid knowledge on ASIC DFT design and verification, including JTAG/IJTAG, MBIST, SCAN, ATPG and post-simulation.
3. Familiar with ASIC design flow, including RTL coding, formal/UPF, synthesis and STA.
4. Experienced in DFT EDA tool usage, such as Tessent mbist, scan, VCS/NC and DC/PT.
5. Fast learning and good communication skills.

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