1.project verificaiton, verify IC development in the area of mobile IC's.

2. Strong verification background for the state of art 1Cs with experience in UVM or OVM.

3. The verification responsibilities will include architecting verification strategies, participating on a team to verify logic designs, and building System Verilog constraint driven test-benches.

4. Candidate should be proficient in planning, constructing test benches and writing sequences, writing functional coverage, writing tests to create test patterns, performing code coverage analysis, and debugging of gate level simulations.

5. Experience with ARM, USB, USB PD, and USB Type-C is a plus.
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Requirements:

Education & Experience:

1.BSEE required,MSEE preferred.

2. Minimum of 4 years (6 years for BSEE) experience for verification of ICs Expertise/Skills

1. Excellent communication and problem-solving skills.

2. Be proficient in Verilog/System Verilog.

3. Experience with the digital design tools is beneficial