工作职责:
1.To take responsibility for TEG layout design and layout including MOS, Cell, process and Reliability monitor etc
2.Complete DRC, LVS, LVL layout verification
3.Well communicate with device, designer and process team to make sure Tapeout on time
任职资格:
1.At least 2 years Semiconductor manufacture experiments
2.Have knowledge in Semiconductor device and logical process flow is must be
3.Experience in layout and verification tools such Virtuoso, skipper, Calibre drc
4.Some experiences in script writing such as Skill, Calibre will be advantageous
5.Require a strong attention to detail and good team player