工作职责:
1.To take responsibility for layout verification, can use verification tool（LVS,DRC,LVL）to check layout drawing error
2. Can make new LDR to solve TEG layout
3. Well communicate with designer and process team to make sure layout correct and ready on time
任职资格:
1.At least 2 years Semiconductor manufacture or layout design experiments
2.Have knowledge in Semiconductor process and design rule is must be
3.Experience in layout and verification tools such as Virtuoso, skipper, Calibre drc
4.Some experiences in script writing such as Skill, Calibre will be advantageous
5.Require a strong attention to detail and good team player