Job Description: 1. Participate in developing layout designs for CMOS sub-micron IPs, including analog, mixed-signal, and foundation IPs, based on circuit design requirements. 2. Complete physical verification and parasitic parameter extraction. 3. Generate data packages according to the company’s design flow.
Qualifications: 1. Bachelor’s degree or above in Microelectronics or Electronics Engineering, or related field. 2. Familiarity with Unix/Linux operating systems and experience in using Synopsys/Cadence/Mentor or related EDA software. Proficiency in scripting languages such as Shell, Skill, Tcl, or Perl is preferred. 3. Prior experience in layout design, familiarity with IC design flow, and knowledge of chip manufacturing processes are preferred. 4. Strong foundation in both analog and digital circuits is preferred. 5. Self-motivated, dedicated, and proactive, with good communication and teamwork skills.