Job Description: 1. Responsible for the backend implementation of digital designs, including layout, routing, timing sign-off, and power sign-off. 2. Collaborate closely with frontend engineers to optimize timing, area, and power, and perform static timing analysis. 3. Optimize and verify the layout of the chip, including parasitic parameter extraction, ECO, DRC, LVS, etc. 4. Perform IR drop analysis and optimize the die size.
Qualifications: 1. Master’s degree or above in Electronics or related field. 2. Previous experience in IC backend automatic layout and routing (including coursework projects). 3. Preferred experience with digital backend tools such as ICC, StarRC, PrimeTime, RedHawk, Calibre. 4. Self-motivated, with good teamwork and effective communication skills in both English and Chinese.