工作职责:
1. Implement DFT structures (internal-scan (stuck-at, at-speed), JTAG, MBIST, hard IP testing structure) in block/chip level design.
2. Generate, simulate and debug the block/chip level test bench.
3. Interface with back-end physical design team to complete timing closure for test related logic
4. Interface with operation team to debug production test-vectors for wafer test and final test


任职资格:
1.M.S. or B.S. degree in EE or equivalent
2.3+ years work experience in DFT design
3. Familiar with chip level DFT design and verification
4. Attend the training course of Functional Safety
5. Logical thinking and sensitive to the problem with good self-study and problem shooting ability

*公司坚持平等原则，公平公正对待不同背景的员工，包含但不限于国籍、性别、宗教信仰、文化背景等方面，提供平等发展机会，构建多元化人才体系
6. Good communication capability and teamwork spirit