职责描述：
根据技术节点要求，设计器件规则并调试器件使之满足目标要求；
优化SRAM，增大margin,提升良率。
与PIE部门紧密配合，按时完成技术节点的开发.
与spice model 部门紧密配合，完成技术节点的spice model.
与 可靠性测试部门紧密配合，完成器件的可靠性验证和改善.
熟悉WAT auto test, bench test.
熟练应用layout 软件，设计device,并会做LO, DRC check.
1. Design device process rule and tune device to meet technology requirement.
2. Optimize SRAM, increase SRAM margin and improve SRAM yield.
3. closely coworking with PIE team, complete technology node development on time.
4. closely coworking with Spice team, complete the spice model of technology.
5. closely coworking with RE team, to improve reliability performance.
6. Be good at WAT auto test, bench test.
7. Familiar with layout softwafer to design device, and check GDS post LO and DRC.
任职要求：
1. 微电子，半导体物理，物理学、电子或材料科学专业本科及以上学位，微电子背景优先考虑
2. 3年以上Device、SRAM设计、PIE、工艺或产品工程相关经验，具有FEOL工艺/器件物理经验者优先.
3. 具有扎实的半导体物理、半导体器件和微电子工艺基础知识；
4. 英语四级及以上，熟练使用office办公软件；
5. 具有良好的沟通协调技巧，抗压能力强，服从部门管理，为人正直。
Job Qualifications：
1. Master degree or above, major in Physics, EE or material sciences, background EE is preferred；
2. At least 3 years related working experience in Device, Integration, SRAM design, Process or Product engineering, experience in FEOL process/device physics is preferred.
3.Solid knowledge of semiconductor physics, device physics and microelectronic process;
4. CET-4 and above, proficient in using office software;
5. Have good communication and coordination skills, strong ability to withstand pressure, obey department management, and be upright.