Job Duties:
Work with ASIC architect to define micro architecture specification of major functional blocks
Utilize your design skill to develop RTL code in Verilog/System Verilog HDL and produce high performance, low power, optimized design netlist using industry standard synthesis tools. Resolve timing issues through static timing analysis
Work with DV engineers to define test plan and coverage analysis, resolve all design issues by debugging with DV engineers in a timely manner
Work with physical design engineers to resolve any issues arising from backend flow requirement, including DFT, power optimization, timing closure, etc.
Participate in pre-silicon validation using FPGA platform, and post silicon bring up on EVB
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Requirement:
BSEE or equivalent is a must, MSEE is preferred
Ideal candidate should have minimally 3-7 years of IC design experience
Familiar with Verilog/System Verilog design flow with industry standard EDA tools
Domain knowledge in networking ASICs, such as Ethernet PCS/MAC layer or higher layer in IP stack, is definitely a plus
Experienced with unix/linux scripting language such as perl, tcl, Python, etc.
Familiar with AHB / APB / Axi protocol, understanding arm architecture and debugger working principle is preferred
Good English communication and documentation skill is a plus
岗位职责
1、制定数字逻辑电路模块的规格文档；
2、运用硬件描述语言（Verilog/System Verilog等）完成数字电路的模块设计；
3、协助验证工程师完成模块验证, 对验证计划提出建议并积极参与验证覆盖率分析。 及时解决模块中的bugs；
4、协助后端设计工程师完成物理实现；
5、参与芯片测试；
任职资格
1、电子、通信及集成电路等专业本科以上学历，硕士学历优先；
2、3-5年及以上工作经验；
3、熟悉硬件描述语言，如Verilog、System Verilog等；
4、熟悉脚本语言，如perl、tcl, Python等；
5、有网络芯片设计经验， 特别是拥有以太网底层电路， 协议栈知识的员工会给与优先考虑；
6、 熟悉AHB/APB/AXI协议，了解arm架构及debugger工作原理优先;
7、具备优秀的团队合作和沟通协调能力。
福利待遇:
1、固定工资、年底奖金、额外绩效奖金、期权激励、晋升培训；
2、五险一金，享有国家规定的法定节假日及带薪年假（年假、婚假、产假、病假）等待遇；
3、周末双休、弹性工作时间；
4、定期团建、下午茶歇、过节福利、团队聚餐、生日蛋糕、定期体检；
5、公司提供免费公寓，环境好；
6、办公环境舒适，地铁10号线直达，附近多个公交站点，交通十分便利。
注：办公地址：浦口。