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Lead Verification Engineer
3-4万
人 · 硕士 · 3年及以上工作经验 · 性别不限2024/08/29发布
五险一金专业培训补充医疗保险补充公积金餐饮补贴定期体检弹性工作年终奖金股票期权

浦口区浦口大道1号新城总部大厦B座23楼

公司信息
Cadence(南京凯鼎电子科技有限公司)

外资(欧美)/50-150人

该公司所有职位
职位描述
Lead Design Engineer – Verification
Location: Nanjing
Position Description:
Specific duties include:
Responsible for verification plan define based on IP design SPEC.
Lead verification team to achieve the coverage driven verification goals.
Verification Test-Bench maintain and development.
Deep understanding on ASIC verification flow, responsible for milestone delivery check

Position Requirements:
Master degree with 2+ years or bachelor with 4+ years as an experienced digital IC verification.
Experienced in successful tape-out of ASIC chips
Familiar to UVM test-bench architecture and experienced on test-bench development.
Self-motivation with communication skills (spoken and written English and Mandarin)
Experienced in coding of SV, Perl/Python, Makefile

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