DESCRIPTION:

- A senior role in physical design team on projects

- Participate in various aspects of physical design, including full chip floorplanning, power/clock distribution, timing optimization, place & route, timing closure, power/signal integrity analysis, and physical verification

- Troubleshoot complicated issues in design and flow, and apply proactive solutions

- Collaborate with RTL, DFT and Circuit designers to ensure the high quality of design implementation and optimization

MINIMUM QUALIFICATIONS:

- BS in Engineering or Science

- Experienced user of EDA tools from Synopsys (DC/PT), Cadence (EDI/EPS/ETS)

- Experience in Clock/Power Distribution, P&R, Timing closure, RC Extraction, and verification on 40nm, or 28nm technology

- 3+ years of experience in above areas

PREFERRED QUALIFICATIONS:

- MS in Engineering or Science

- Knowledge in 20nm or FinFET/FDSOI technology, circuit design, and package design

- Experience in physical verification tools from Mentor (Calibre)

- Proficiency in Perl, TCL and Makefile scripts




岗位职责描述：




● 物理设计团队的高级职位

● 负责rtl2gds全流程工作，包括综合，时序约束编写，形式验证，布局和电源规划，时钟树综合，时序优化收敛，电源/信号完整性分析以及物理验证等

● 与前端，DFT和电路工程师紧密沟通合作，确保完成高质量物理设计工作

最低要求：



● 学历本科及以上

● 电子、电气工程、计算机、微电子相关专业

● 熟练使用Synopsys（DC / PT/ FM），Cadence（EDI / ETS/ GENUS）和Calibre等主流eda工具

● 3年（硕士）或5年（本科）以上物理设计经验

优先资格：

● 具有先进工艺节点（20nm、10nm等)物理设计经验

● 具有丰富的超大规模soc逻辑综和sta经验，精通sdc文件

● 具有复杂物理设计流程开发经验

● 具有较强的脚本（tcl、perl、makefile和csh等）编写能力







本职位可在以下两个工作地点上班：

无锡：无锡市滨湖区无锡市滨湖区建筑西路777号A1栋17楼

上海：上海市徐汇区宜山路900号A座1601室