1. Responsible for IPs/SOC design verification/regression
2. Creat verification test plan, develop verification enviornment and write test cases
3. Co-work with other teams for simulation and debug support


岗位要求：
1. 1+ years working experience in IPs/SOC design verification
2. Knowledge of Verilog, System Verilog, C/C++ is a MUST
3. Self-motivated, with good communication skill and learning ability
4. Knowledge of script languages such as TCL, Makefile, Perl, Python is a plus
5. Knowledge of AHB/AXI bus protocol and standard peripherals or high speed interfaces is a plus
6. Knowledge of Video codec is a plus