Responsibilities ? Design GPIO library and customization IO, provide instruction on layout. ? Design ESD protection circuit for Analog/RF IP. ? Provide ESD protection strategy/guideline, pad cell assignment and ESD review for whole chip. ? ESD/Latchup test and Failure Analysis.
Requirements 1. Over 3-years of related working experience in IO & ESD design. 2. M.S. in EE or equivalent. 3. Knowledge in device physics, process, and physical layout. 4. Deep understanding of IO ESD/Latchup protection. 5. Experience on timing model and IBIS model. 6. Experience on DDR/SD/eMMC/LVDS IO is preferred. 7. Self-motivated, good communication skills and team work spirit are a must.