Job Description:
- Block, IP and SoC level DFT implementation (MBIST, Scan, JTAG, analog/IP test etc.) and RTL coding integration;
- Participate in test spec/plan definition, complete DFT design document and signoff DFT review checklists;
- Test patterns/vectors generation and verification;
- Interface to backend team on physical design and DFT timing closure;
- Co-work with test engineers on ATE patterns bring-up, debugging and failure analysis;
- SoC DFT quality sign-off, DFT constraint generation, STA, ECO and formal check.

Qualifications:
- hands on DFT design and integration experience (MBIST, DC&AC Scan, Analog IP test circuit design, JTAG&BScan, ATPG and test pattern verification);
- expertise with various kinds of DFT tools including Mentor, Synopsy, Cadence, Syntest etc.
- strong digital RTL design and verification ability; experience in pre&post layout gate level simulation;
- experience in Synthesis, STA and formality will be plus;
- proficient in Perl, tcl and shell programming;
- BSEE degree or above;
- good team work spirit.