岗位职责：
1) 基本的底层电路设计/优化，例如 电平触发器/延触发器/加法器/移位寄存器
2) 混合信号电路设计例如电平转化电路/正反相位同步电路
3) 理解/设计/改良DRAM的读写数据通道
4) 管理FIFO的控制，计算合理深度
5) 深度理解spec，在不损失电路性能的情况下优化电路的功耗；
6) 理解JEDEC中关于AC Timing的定义并检测fullchip仿真的相关数据，提供改善方案
7) 理解/设计/改良DRAM 命令/刷新/training/相关的电路设计；
8) 在前仿和后仿中检测关键的AC参数并完成相应的checklist；
9) 检测电平触发器/延触发器的建立保持时间
10) 为所负责的模块建立合理的可trim选项以提高良率，弥补工艺偏差带来的不足


岗位要求：
1) 熟悉spice级别的仿真
2) 具有CMOS电路基础知识
3) 熟悉电源网络分析工具
4) 熟练使用EDA仿真工具
5) 熟悉门级数字电路的设计方法熟悉EDA后仿真工具
6) 熟悉perl/python者优先

Job Responsibilities：
1) Basic underlying circuit design/optimization, e.g. level flip-flop/delay flip-flop/adder/shift register
2) mixed signal circuit design, e.g. level conversion circuit/forward-inverse phase synchronization circuit
3) understanding/design/improvement of read/write data channels of DRAM
4) managing FIFO control, calculating reasonable depth
5) deeply understanding spec, optimizing circuit power consumption without losing circuit performance;
6) Understand the definition of AC Timing in JEDEC and detect the relevant data of fullchip simulation to provide improvement solutions
7) Understand/design/improve DRAM commands/refresh/training/related circuit design;
8) Check the key AC parameters in the front imitation and the back imitation and complete the corresponding checklist
9) Detect the establishment and hold time of level flip-flop/delay flip-flop
10) Establish reasonable trim options for the responsible module to improve the yield and make up for the shortcomings caused by process deviations

Job Qualifications：
1) Familiar with spice-level simulation
2) Have basic knowledge of CMOS circuits
3) Familiar with power network analysis tools
4) Proficient in using EDA simulation tools
5) Familiar with gate-level digital circuit design methods Familiar with post-EDA simulation tools
6) Familiar with perl/python is preferred