岗位职责：
1) 基本的底层电路设计/优化，例如 电平触发器/延触发器/加法器/移位寄存器r
2) 混合信号电路设计例如电平转化电路/正反相位同步电路
3) 理解/设计/改良DRAM的读写数据通道
4) 理解/设计/改良DRAM 命令/刷新/training/RHR相关的电路设计
5) 理解JEDEC中关于AC Timing的定义并检测fullchip仿真的相关数据，提供改善方案
6) 在前仿和后仿中检测关键的AC参数
7) 检测电平触发器/延触发器的建立保持时间

岗位要求：
1) 熟悉spice级别的仿真
2) 具有CMOS电路基础知识
3) 熟悉EDA后仿真工具
4) 熟悉perl/python者优先

Job Responsibilities：
1) Basic cmos logic design such as latch/flipflop/full adder/shift registor
2) Mix signal circuit design such as translator and phase splitter
3) Understanding and design DRAM data path structure
4) Understanding and design DRAM command/refresh/training/RHR
5) Understanding JDDEC spec and run fullchip pattern to check the spec items
6) Critical timing check with pre/post layout netlist
7) Setup and hold timing check for critical latch/flipflop

Job Qualifications：
1) Finesim/hspice and other spice level simulation
2) Good knowledge on cmos circuit design
3) Familiar with EDA post simulation tools
4) Perl/Python script is plus