Responsibility （工作职责）:
Use various software environments for the behavioral modeling and verification of complex mixed-signal integrated circuit systems
使用各种软件环境进行复杂混合信号集成电路系统的行为建模和验证
Design integrated circuit blocks such as PLL, amplifiers, comparators, bandgap circuits, oscillators and analog-to-digital converters
设计集成电路模块，如 PLL，放大器，比较器，带隙电路，振荡器和模数转换器
Validate datasheet specifications via top-level simulations
通过顶层仿真验证性能参数
Verify operation of new products in laboratory testing, including designing required test hardware and software
通过实验测试等不同途径来验证新产品的功能，包括设计所需的测试硬件和软件
Evaluate and debug circuits at the wafer level
在晶圆阶段评估和调试电路
Qualifications （职位要求）:
EE Master or Bachelor’s degree and at least 3 years of Analog design experience
电子工程硕士或学士以及至少 3 年的模拟设计经验
Experience with schematic entry and layout software, integrated circuit modeling, and circuit simulation using SPICE-like simulators
具有使用 SPICE 仿真器的原理图输入和布局软件，集成电路建模和电路仿真的经验
Familiarity with UNIX-based operating systems. Familiarity with any of the following software tools is beneficial: Cadence Analog Design Environment, Verilog, Verilog-A, MATLAB, Simulink, and LabVIEW
熟悉基于 UNIX 的操作系统。 熟悉以下任何软件工具都是有益的：Cadence 模 拟设计环境，Verilog，Verilog-A，MATLAB，Simulink 和 LabVIEW
Excellent communication, documentation, problem-solving and analytical skills
出色的沟通，文档，解决问题和分析能力
Familiarity with laboratory procedures and basic electronic lab equipment, such as oscilloscopes, voltmeters, and soldering equipment
熟悉实验室程序和基本的电子实验室设备，如示波器，电压表和焊接设备
工作地点: 南京、上海