Responsibilities:
1.Participate in chip and block level DFT architecture definition.
2.Implement basic DFT schemes, including scan, boundary scan, LBIST，SSN，Mem BIST and IST.
3.Verify all DFT logics and test patterns with simulation
4.Test modes static timing analysis
5.Participate in ATE bring-up and debug the DFT patterns on ATE.


Requirements/Qualifications:
1.Either Bachelor or Master degree, 2+years related experience required.
2.Good understanding of the General DFT methodology such as BIST, SCAN, JTAG and ATPG
3.Be familiar with basic Mentor/ Synopsys DFT flow and tools
4.Experience in developing constraints for synthesis/STA
5.Multi-mode, multi-corner STA experience, Understanding Sign-Off Checks