THE PERSON:
· Strong analytical/problem solving skills and pronounced attention to details.
· Must be a self starter, and able to independently drive tasks to completion.
· Strong interpersonal and communication skills.
· Strong responsibilities and team spirit.

KEY RESPONSIBILITIES:
· Responsible for industry leading IP Synthesis/Formal/STA.
· Responsible for industry leading IP LINT/CDC/VSI.
· Responsible for industry leading IP regularly regression.
· Responsible for function ECO implementation and LEC/DRC check.
· Work with global IP teams to guarantee IP delivery quality.
· Work with multiple global SOC teams to implement Tile.
· Work with multiple global SOC teams to accomplish successful tapeout for AMD Sever/Client/dGPU/SCBU products.
· Work with front-end integration team and physical design team on timing closure.
· Co-ordinating design and implementation activities.

PREFERRED EXPERIENCE:
· Minimum 5 years of experience with Verilog a MUST.
· Familiar with front-end design flow.
· Experience on synthesis, timing analysis and formal verification.
· Excellent knowledge of verilog and a scripting language; experience with Perl and TCL is a plus.
· Low power experience is a plus.
· High speed design experience is a plus.
· Industry Serdes design experience is a plus.

ACADEMIC CREDENTIALS:
Bachelor, Master's degree in Electrical or Computer engineering.