Job Description:
职位描述:
Delivers ASIC implementation flows for all the projects. You'll be working with the digital team and analog team of the back-end implementation flows, such as physical verification and other related flows.
为所有项目提供ASIC集成流程。您将与数字后端工程师团队和模拟版图工程师团队一起完成后端集成流程，例如物理验证和其他相关流程。
Duties:
职责:
Integrate the final tape-out database.
合成最后流片的数据。
Responsible for all the final tape-out physical verification. (DRC LVS ERC violation check)
负责所有最后流片的物理验证。(DRC LVS ERC等检查)
Responsible for all the tape-out related technical documents.
负责所有流片的相关技术文档。
Work with different department to accomplish the tape-out through the beginning till the end.
与不同部门合作完成流片的全过程。
Requirements:
需求:
Experience in layout skills.
有Layout的经验。
Experience in Unix/Linux system. Programming and scripting - Shell scripts, Python, TCL, SKILL, PERL.
Experience in creating VLSI CAD flows and automation scripts is a plus.
熟悉Unix/Linux系统。会使用Sherll/Python/TCL/SKILL/PERL编程和脚本。
有创建超大规模集成电路CAD流程和自动化脚本的经验者优先。
Experience in one or more back-end ASIC flows (Place-and-Route, Floorplan, Layout, DRC/LVS Physical verification) and usage of related EDA tools.
熟悉一个或多个ASIC流程经验(布局布线，规划，版图，DRC/LVS，物理验证等)和使用相关EDA工具的经验。
Experience in top-level chip assembly flows is a plus.
有顶层芯片集合流程经验者优先。
Good at reading and writing in English. Willing to deal with English technical documents. Good verbal communication in English is a plus.
良好的英语读写能力。愿意处理英文技术文件。良好的英语口语交流能力优先。
Good at Microsoft Word, PPT and Excel.
熟练使用Word、PPT、Excel软件。
Good in communication and be responsible at work.
对工作认真负责且具有良好的沟通能力。
Bachelor degree in EE , microelectronics or equivalent experience.
电子工程、微电子或相关专业本科学历。
Good understanding of VLSI design and fabrication process. Fab background is a plus.
很好的理解超大规模集成电路设计和制造流程。有代工厂背景尤佳。