工作职责:
1. Build test plan and verify the function of design, support gate level functional verification, run coverage and regression. Analyze coverage gaps and devise strategy to fill coverage holes
2. Build IP verification environment
3. Interfacing EDA vendors for modern verification methodology, access vendors' design verification capabilities and convergence
4. work in lab to do module level validation and FPGA verification
5. Other tasks assigned by manager
6. Scripts study
任职资格:
1. Strong analytical, and problem solving skills;
2. Good knowledge of verification methodology and using random stimulus along with assertion-based verification;
3. Able to write C code to model RTL blocks for simulation and verification;
4. Able to write Verilog or system Verilog to create test bench, UVM is a plus;
5. Knowledge of formal verification is highly desirable, but not required;
6. Knowledge in languages relevant to the verification including Unix Scripting, Perl and Tcl is strong plus;
7. Knowledge of Video/ISP/SOC is a plus;
8. Good communication skills, especially in technical writing and reporting;
9. Self-motivated and ability to excel in a team environment.