工作职责:
1. Be responsible for the IP schematic design and simulation.
2. Instruct layout engineer to complete the physical implementations.
3. Can use the test instrument such as: oscilloscope, voltage meter to do the test.
任职资格:
1.M.S. in Electrical engineering or equivalent
2.1 or more years of analog circuit design experience such as ADC/DAC, POR, LDO, PLL design
3.Experience of Spice simulation and mixed-signal simulation
4.Strong physical layout knowledge and parasitic component understanding is essential
5.Process and device physics knowledge is preferred.