工作职责：
?Plan the verification of complex digital design blocks by fully understanding
the design specification and interacting with design engineers to identify
important verification scenarios；
?Create verification environment or test bench using System Verilog, UVM
and/or System C；
?Identify and write all types of coverage measures for stimulus and
corner-cases；
?Debug tests with design engineers to deliver functionally correct design
blocks；
?Responsible for SoC's IP Level and Top Level verification, Pre-sim and
Post-sim verification as owner;
?Build test cases, analyze validation results, and improve validation quality；
?Close coverage measures to identify verification holes and to show progress
towards tape-out。
任职要求：
?BS degree or equivalent practical experience. MS in EE or CS is preferred；
?3+ years of relevant experience on IP based SoC verification；
?Familiar with Tilelink/AMBA/AXI bus protocol；
?Experience with verification methodology such as UVM/OVM/VMM/System C/C++；
?Experience with the full verification life cycle and experience with
functional coverage；
?Experience with function verification for common SoC building blocks and
verification ip: I2C/ UART / SPI /I2S/USB, etc；
?Strong problem solver, communicator and team player；
?Good people and communication skills in Mandarin and English；
?Scripting skills in Perl, tcl, shell, etc；
Big Plus：
?Experience in SoC verification with ARM MCU/CPU and DS；
?Experience in validation/verification for RISC CPU/MCU core design；
?Experience in coding and simulation of chisel；
?Experience with System Verilog SVA and Functional Coverage。