Work with analog/digital ASIC design team for new product development;
61 RTL Design and verification of digital design in mixed-signal ICs;
61 Perform backend digital design (logic synthesis, formal check, define design constraints
for place & route, perform timing closure, DFT);
61 Support system, test & product team with chip debugging, failure analysis,
characterizations and product release efforts.

Qualification Requirements：
61 Bachelor/Master degree or above in EE or related field;
61 At least 5 years’ experience in digital IC design;
61 Good knowledge of RTL design with Verilog or System Verilog;
61 Good knowledge of different industry-standard interface design;
61 Experience or knowledge to handle different type of embedded memories (SRAM, OTP,
Flash etc);
61 Knowledge of embedded processor and digital processing is preferred;
61 Good knowledge of front-end design flow: Simulation, Synthesis, DFT, STA, formal check
61 Knowledge or understanding of transistor level schematic design is a plus;
61 Knowledge of modeling analog devices is a plus;
61 Mixed signal design knowledge is preferred;
61 Good language and communication skills in English for both spoken and written;
61 Highly organized and self-motivated;
61 Ability to work well with teammates (locally or remotely) in a fast-paced professional
environment