Responsibilities:
-Implementing from Synthesis to GDSII that includes synthesis, P&R, timing signoff, physical signoff and all variety check for Higher QoR.
-Power optimize based on power analysis result.
-Cooperate with designers on RTL issues which relative to back-end timing closure and congestion solve.
-Analyze the design and the flow to improve the PPA.

Qualifications:
-Understanding the static timing analysis, synthesis, logic optimization, placement, routing, CTS, custom layout, DRC, LVS concepts.
-Familiar with Cadence/Synopsys/Mentor Back-end EDA tools, such as GENUS, ICC, INNOUVS, PT, Calibre.
-Good programming skill, capable of writing Tcl/TK/Python.
-Good verbal and written communication skill in English.
-Previous back-end project experience is a plus.
-Familiar with RTL Design in Verilog or DFT concepts is a plus.