工作职责:
1. Define chip level DFT test spec and test structure.
2. Be responsible for DFT flow/methodology evolvement, DFT logic implementation and verification, including MBIST, Scan, Boundary Scan and IP test.
3. Be responsible for pattern generation along with pre-layout simulation/post-layout simulation of each DFT test item.
4. Be responsible for DFT SDC release and check, along with DFT related STA, power and IR task forces.
5. Co-work with production and testing team, complete ATE bring up/pattern tuning and yield improvement work of all DFT test items and drive low or even zero DPPM.
任职资格:
1. Major in EE or related. Master degree with 4~6 years’ experience in DFT-related areas.
2. Solid knowledge on ASIC DFT design and verification, including JTAG/IJTAG, MBIST, SCAN, ATPG and post-simulation.
3. Familiar with ASIC design flow, including rtl coding, formal/UPF, synthesis and STA.
4. Experienced in DFT EDA tool usage, such as Tessent mbist, scan, VCS/NC and DC/PT.
5. Fast learning and good communication skills.