Job Description :
-Chip level physical design implementation from Netlist2GDSII APR flow
-Chip level BE implementation/signoff plan & review with customer co-work
-Chip level design/IP Macro/IO floorplaning
-Chip level power design/plan, analysis & IRDrop signoff
-Clock distribution analysis and high speed/performance CTS flow generation
-Place & routing, timing closure and timing signoff
-Physical design verification (DRC/LVS/ERC/DFM)
-Design flow implementation with low power UPF/CPF

Candidate requirements:
-BSEE/ME/CE, MSEE/ME/CE is preferred (电子工程／微电子／通讯工程）
-Hand-on experience in Synopsys (ICC2/FC/PT/StarRC) or Cadence (Innovas) & full chip backend implementation flow are preferred
-User of Perl or TCL is preferred
-English communication skill
-BE experience > =5 years