Job description
Be responsible for the development of digital circuit design in ASIC or Mixed Signal products.

Define internal design spec basing on marketing datasheet

Responsible for RTL design & simulation, logic synthesis, static timing analysis, formal check

Support FPGA verification and Silicon Validation

Qualification Requirements
Bachelor degree or above in EE

Minimum 5 years ASIC logic design experience

Familiar with HDL design with Verilog or VHDL

Familiar with ASIC design and verification flow

Familiar with scripts of TCL, Perl, etc. is a plus.

A successful product development from specification to GDSII experience is a plus

Good communication skills and team work

It will be a big plus if relative experience on one or more of DSP, Dynamic system feedback control ,Smartcard or memory control.

高级ASIC设计工程师
主要职责：
负责专用集成电路或混合信号芯片中数字电路的RTL设计开发工作

负责设计文档的撰写

负责逻辑综合，静态时序分析，一致性验证等

参与测试和仿真向量生成，FPGA相关验证支持

参与芯片的样品调试和量产测试.

任职资格：

硕士学历，电子工程，微电子，或相关专业

5年以上数字电路设计经验

熟悉ASIC 流程，熟悉VHDL/Verilog

具有数字、模拟电路的基础知识，学习能力强；

良好的沟通能力及团队合作精神

有成功产品完整开发和流片经历

优先考虑有以下相关产品经验之一：存储器，智能卡，自动控制（PID）。