关键要求：电子工程硕士，1年以上模拟设计经验，擅长PLL，CDR，TIA，Laser Driver，Equalizer，SerDes等任一方向均可

Job Responsibilities:
1. Design, analyze and implement high-performance (>10GHz) PLL, wireline amplifiers, CDR, SERDES, PLL, PAM4, TDCs, TOF, low-noise amplifiers, transmitters, power-amplifiers and power-drivers, or other baseband circuits like LDO, temp sensor, ADC, Filters, etc.
2. The design of high-frequency (multi-gigahertz) and high-precision clocking and analog circuits.
3. Use EDA tools (Cadence, Mentor) to run simulation and function verification.
4. Guide layout engineer to optimize layout.
5. Chip debug and testing individually and with the team.
6. Other tasks assigned by line manager.

Qualifications:
1. MSEE with at least 1 year experience. Excellent fresh graduates are considered.
2. Hands-on design experience
3. Experience in Cadence EDA tools.
4. Team player with good communication skills.
5.Experience with multi-gigahertz high-speed interface like SERDES transmitter/receiver, or TIA/PLL/CDR/LNA, ToF, Temperature Sensor, high-precision/high-speed ADC or power management IC is highly preferred.
6. Experience in Cadence EDA tools.
7. Team player with good communication skills.