Summary
Key member of the Tensilica DSP team within Cadence, responsible for design verification of DSP based hardware products as part of families of Tensilica DSPs and hardware accelerators, targeting various application domains such as computer vision, AR/VR, audio/voice, Radar, AI or ADAS/AD.

Be part of an agile team with experts in DSP architecture, design, implementation, and HW/SW verification. Gain understanding of the DSP algorithms and mathematical functions being implemented. Architect and implement verification environments and tests to ensure that the implementation is correct, there are no functional bugs, and the performance criteria were met. Design, implement and maintain large scale regression frameworks that improve quality and project execution time.


Job Responsibilities
Maintain the ISA verification test bench and test template
Define and manage verification/test plans
Create the reference models of DSP instructions with C according to the spec
Collaborate with architecture/design team to understand the specification DSP algorithms and mathematical functions.
Define and develop detailed test plans.
Develop tests in C/C++ to create a behavioral model of the DSP functions, using fixed point or floating point arithmetic.
Develop and maintain extensible/large scale regression flows and infrastructure, including tools for aggregating metrics and trending.
Create the reference models of accelerators with SystemC according to the spec
Debug the DSP instruction and accelerator tests and collaborate with design engineers
Analyze the functional and code coverage


Job Qualifications
Master degree in CS/CE, EE, Telecom or equivalent, at least 6 years industrial relevant working experience
Strong knowledge of computer architecture and processor design
Proficiency in programming languages like C/C++, assembly, Verilog, System Verilog
Skillful with version control tools
Familiar with scripting languages like Perl, Makefile
Familiar with design verification methodology
Familiar with ISA simulator and debugger
Self-motivated with excellent planning, interpersonal, and communication skills
Excellent oral and written English


Addition Skills
Familiar with SystemC or SystemVerilog
Familiar with UVM
Processor design/verification experience is highly desirable