JD：
带领5~8人team并协助团队完成block/top level的后端设计（physical design）；
ASIC或SoC芯片的模块级和顶层级物理设计；
模块或芯片系统级电源地网络设计和验证；
低功耗物理设计和验证；
前后端时序优化，芯片级时序验证；
模块和顶层版图物理验证，DRC/LVS/ERC等；
完成netlist到GDSII的全流程工作：
floorplan，power planning，place&route，cts, timing closure，power analysis，physical verification，ECO；


Requirements：
大学本科8年以上相关经验，硕士6年以上相关经验；
微电子／电子工程／通信工程等相关专业 ；
相关的IC后端设计工作经验或tape-out成功经验；
熟悉PNR，STA，DRC，LVS、DRC等流程；
熟悉EDA工具，如 ICC2，Innovus, Primetime, Calibre, redhawk等；
熟练使用tcl/perl/phython等；
良好的英文沟通能力；
团队带领以及协调能力；






公司简介：
Founded in 2018, founder has 20 years’ IC industry experience, worked for top IC companies like IBM, AMD, Synopsys, Verisilicon, SYNAPSE and Intel as leader, has long-term, solid and positive relationships with all patterners. And the team members most have 10+ years’ IC design experience, merging with the fastest growing technology both in ASIC and SOC field, patterner including AMD, ADI，GlobalFoundries, HiGon, ZTE，GPT, SYNAPSE，MICROPILOT…
Mass production including diverse productions: 7nm/14nm GPU design chip, 28nm high-end graphic chip, 28nm mobile phone chip, 28nm low-power graphic chip, 40nm networking chipset, 55nm mobile chip… we also provide professional, effective and practical consult service for newly established company.
Now we have Beijing, Shanghai, Nanjing, Chengdu sites, to support flexible and high-efficiency working model both for patterner and employee.