1.Perform block level and Top level,Full custome RF and analog layout;
2.Perform layout verification DRC/ERC/LVS(Calibre tool;
3.Team work with Circuit designers,optimize layout.


任职要求：
1.Bachelor or above degree with 2 years experiences in CMOS IC full-custom layout;
2.Experiences in Mixed signal/analog/RF layout;
3.Familliar with layout skills and knowledge;
4.Familiar with Cadence IC layout and Calibre verification tools;
5.Famillar with 55nm 40nm CMOS process and design rule;
6.Famillar with ESD/Latch up/antenna and related layout solutions;
7.Good teamwork and communication.