ob Description：
understanding the digital designs(Chip & IP);
Developing verification and regression plans;
Designing and developing verification environment;
Running RTL and gate level simulation/regression;
Coworking with Design&FPGA team;
Code/functional coverage development, analysis and closure;
Job Qualification：
Minmum of 5 years verification experience;
Knowledge in asic design process and verification tools/env (UVM);
Familiar with design and verification languages(verilog, System Verilog, SVA etc.);
Familiar with Simulation & Debug Tools(VCS, Verdi, etc.);
Familiar with ASIC Design Flow;
Scripting skills (perl, tcl, makefile, Python etc.) is a plus;
Experience in SOC chip level verification, including test plan and testbench development, test case development;
Additional qualifications include: Good Ic verification skills and basic knowledge of logic or circuit desing, good communication and problem solving skills;