Role:

· Physical verification work in block and chip level.

· Drive the sign-off physical convergence.

Responsibilities

· 5~8 Years of relevant experience in physical verification.

· Should have expertise in 16nm / 12nm / 7nm process nodes.

· Tapeout sign-off experience is a must using industry standard signoff tools like Calibre,
ICV. Experience at sub
system level signoff is must, chip signoff experience is preferred.

· Hands on experience into Physical verification at block and chip level DRC, LVS, DFM,
Antenna, ERC, PERC, ESD.

· Understanding of basic device physics skills.

· Working knowledge of Innovus or ICC2.

· Physical verification flow automation exposure will be an added advantage.