职位描述：
1. 设计开发深亚微米下的基础IP电路，包含标准单元，存储器和用于优化芯片性能功耗面积的定制电路。
2. 指导版图工程师，并基于后仿真结果协助其优化版图。
3. 库的特征化以及产生数字设计流程所需的设计模型，包含Synopsys liberty model，verilog等。
4. 设计标准单元/存储器/IO的电路测试芯片，并协助测试工程师进行测试。

职位要求：
1. 电子工程等相关专业硕士以上学历，三年以上工作经验。
2. 掌握电路设计并有实际项目经验，同时具备扎实的器件物理知识。
3. 熟悉脚本语言和行为模型，比如Tcl，Perl，Verilog等，并具备相关经验。会使用Cadence/Synopsys/Mentor的主要EDA工具。
4. 具备自我激励意识，良好的沟通能力和团队合作精神。


Job Descriptions:
1. Design and develop deep sub-micron foundation IP circuits including standard cells, memory and customization cells for chip PPA optimization
2. Guide layout designer, assist in layout optimization based on post-layout simulation results
3. Characterize and generate design models supporting major EDA design flows including verilog, Synopsys liberty model etc.
4. Design test chip testing circuits for STD/MEM/IO libraries and assist in testing.

Requirements:
1. Minimum MS degree in EE or related majors with minimum three years experiences.
2. Knowledge and project experience on circuit design with strong background on device physics.
3. Familiar and hands-on experience in script language and behavior model, ie,Tcl, Perl, Verilog, etc. Experiences on Cadence/Synopsys/Mentor's EDA tools
4. Self motivated, good communication and team work skills are a must.