Job Description: 1) Understanding and design row/col redundancy 2) Understanding and design row/col decode sequency 3) Discuss and design array structure 4) Understand and check the critical array timing 5) Build accurate array model for array timing check 6) Do sense amp and sub word line driver design for new array structure 7) Cowork with refresh/RHR designer and carry out address calculation for RHR
Job Qualifications: 1) Finesim/hspice and other spice level simulation 2) Good knowledge on cmos circuit design 3) Familiar with EDA post simulation tools 4) Perl/Python script is plus