岗位职责：
1) 理解并设计DRAM矩阵的行和列解码电路
2) 理解并设计DRAM矩阵的行和列冗余逻辑
3) 理解并改良/设计DRAM矩阵架构
4) 建立精准的DRAM矩阵模型并测量JEDEC中array相关的关键时间参数
5) 改良/设计DRAM矩阵的小信号灵敏放大器以及驱动电路
6) 协同RHR/刷新电路设计工程师完成DRAM矩阵中相对应的逻辑电路

任职要求：
1) 熟悉spice级别的仿真
2) 具有CMOS电路基础知识
3) 熟悉EDA后仿真工具
4) 熟悉perl/python者优先

Job Description:
1) Understanding and design row/col redundancy
2) Understanding and design row/col decode sequency
3) Discuss and design array structure
4) Understand and check the critical array timing
5) Build accurate array model for array timing check
6) Do sense amp and sub word line driver design for new array structure
7) Cowork with refresh/RHR designer and carry out address calculation for RHR

Job Qualifications：
1) Finesim/hspice and other spice level simulation
2) Good knowledge on cmos circuit design
3) Familiar with EDA post simulation tools
4) Perl/Python script is plus