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硬件工程师(MJ012053)
2.5-3万
人 · 本科 · 5年及以上工作经验 · 性别不限2024/12/29发布
五险一金补充公积金弹性工作双休WLB

浦东新区

低价好房出租>>

张江集电港-11号楼

公司信息
施耐德电气(中国)有限公司

外资(欧美)/10000人以上

该公司所有职位
职位描述
Description - External
Responsibilities:
1) Work with project design leader to complete design definition and hardware specification.
2) In charge of hardware (Digital, Analogue or FPGA) schematic design/debug, working with eCAD Engineer to complete PCB layout design.
3) Supporting for all cross-functional teams during R&D phase.
ú Work with Software board bring-up in lab.
ú Work with Quality for all delivers (ECSQ etc.)
ú Work with Purchaser for low BOM Cost
ú Work with Industrialization/EMS plant for EP/MP/PR Blank PCB/PCBA manufacture
ú Work with Certification to solve all EMC/EMI issues.
ú Work with Validation team to solve all issues.
4) Work with a cross-functional global team in multiple time zones.
Qualifications - External
Qualifications
1) Strong interpersonal skills is a must.
The position requires closely working with eCADs, Mechanical CADs, software, certification, Industrialization, validation, internal Schneider Plant as well as outside vendors (EMS plant etc.).
2) Digital/Analogue embedded system design capability.
Mandatory:
ú Familiar with Mentor or Cadence tools.
ú Experience with complex processor (for example: ARM, POWER PC or SOC etc.) and high speed embedded hardware system design.
ú Familiar with SI, PI, derating, power budget estimation, thermal analysis etc.to secure quality of deliveries.
ú Experience with analogue signal chain design, data acquisition design.
ú Capability of C coding for debugging.
ú Familiar with solving EMC/EMI related issue.
ú Familiar with Blank PCB/PCBA manufacture.
ú Strong lab skills with hands on soldering components, operating oscilloscopes, logic analyzers, signal generators etc.
Optional:
ú Experience with power supply design is a plus.
ú Be a main designer in one or more project is a plus.
ú Familiar with uboot/Linux Porting based on POWER PC or SOC is a plus.
ú Familiar with PRP/HSR/RSTP or IEEE1588 is a plus.
ú Familiar with Design of Current/Votage Transformer is a plus

3) FPGA design capability
Mandatory:
ú RTL(Register Transfer Level) design, familiar with ISE, Quartus, Modelsim tools;
ú Test bench development and design simulation;
ú Static timing analysis, resource estimation and power estimation analysis;
Optional:
ú Experience with System on chip (SOC) and NIOS II design is a plus.

4) Must be a self-motivated team player with good oral and written English communication skills, and strong sense of ownership.
5) BS, MS(Preferred) in Electrical Engineering, at least 5-8 years for dedicated hardware development, board bring-up experience.

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