Intel Dalian Memory Technology and Manufacturing (DMTM) is high-volume manufacturing memory fab in Intel China working on leading edge 3D NAND product. Intel and SK Hynix have an agreement for SK Hynix to acquire Intel's NAND memory and storage business. and Intel will continue to manufacture NAND wafers at the Dalian memory manufacturing until the final closing expected to occur in March 2025. Intel DMTM will continue to build on the success of our NAND technology at a greater scale, play a larger role in supporting our customers.
Key Responsibilities:
Lead the design and development of data and I/O circuits for 3D NAND Flash memory products, focusing on achieving higher I/O speeds and optimal performance. Architect and construct robust high-speed I/O solutions, ensuring they meet stringent area, power, and performance requirements within process limitations. Oversee front-end and back-end high-speed I/O testing in post-silicon phases, ensuring product integrity and performance. Collaborate closely with layout designers to optimize circuit area and performance, adhering to best practices in high-speed circuit design. Interface with cross-functional teams to address and resolve product-level challenges, ensuring seamless integration and functionality
This position is associated with the sale of Intel's NAND memory and storage business to SK. This transaction will enhance the resources and potential of the business' storage, and you will be joining a world-class team that will transition to lead the SSD business at SK group. We will keep you informed updates and steps related to this transaction.
Qualifications:
A Master or above degree in Electrical Engineering or a related field, with at least 3 years of experience in I/O design. Proven expertise in RX, TX, and I/O pipeline circuit design and debugging. Hands-on experience with DDR I/O interface training and calibration techniques. A deep understanding of high-speed I/O circuit layouts and the intricacies of their design. Knowledge of high-speed I/O operational mechanisms and associated reliability concerns. Experience with power and signal integrity challenges in high-speed I/O domains. Exceptional communication skills, with the ability to articulate complex technical concepts to peers and cross-functional teams.
