This position is for RTL designer role in OIS development team. The position involves in-depth understanding of the ASIC design flow from RTL to GDS2 and the challenges posed by advanced technologies. The successful candidate will possess detailed understanding of RTL design, synthesis, static timing analysis, formal verification,clock domain crossing, and low power techniques. Knowledge and experience of micro process integration is required.
【Skills/Experience】
1. Must have 10+ years of practical experience with details of RTL development including: functional and structural RTL design, design partitioning, simulation and regression, collaboration with design verification team.
2. Must have good familiarity with latest RTL languages and tools, including: simulation systems (e.g. VCS), synthesis tool (e.g. Design Compiler), static timing tools (e.g. Prime Time), Linting tools, CDC tools, UPF, code coverage, System Verilog Assertion, etc.
【Experience with the following area is highly desirable】:
1. Strong processor architecture knowledge (e.g. ARM, RISC-V)
2. Microarchitecture implementation
3. Microprocessor and analog IP integration
4. BUS matrix implementation and integration
5. Clock, power management, reset design and integration
6. Low power design
【Essential duties and responsibilities】:
1. Develop RTL for multiple logic blocks of an MCU-based ASIC
2. Run various frontend tools to check for linting, clock domain crossing, synthesis, etc.
3. Work with physical design team on design constrain and timing closure
4. Work with verification team to collaborate on test plan, and coverage closure
【Basic Qualifications】:
1. Master’s degree in Electrical Engineering or related field
2. 10+ years of RTL development experience with a record of taping out production silicon
3. Experience with design development using Verilog/SystemVerilog
4. Experience in defining microarchitecture from architecture guideline and model analysis
5. Experience in PPA and trade-offs
6. Proficient in design methodologies and EDA tools
7. Experience working with Synthesis, timing closure, and design constraints
8. Excellent problem-solving and debugging skills
9. Ability with work collaboratively in a team environment and communicate technical ideas effectively
【Preferred Qualifications】:
1. Experience with RISC-V
2. Experience in debugging system-level issues
3. Experience in entire design flow from architecture to final silicon
4. Good programming skills in C/C++ and scripting skill in Python, Tcl or Perl
5. 10 years or more of practical experience
6. Experience with wide variety of low power design techniques
7. Working experience with industry standard buses like AMBA AXI, AHB, ABP
8. Experience in integrating 3rd party IP blocks, building top level modules, defining clock domains and
power domains
9. Knowledge of FPGA and emulation platforms
10. Knowledge of SoC architecture
11. Excellent verbal and written communication skills