任职资格
The candidate is preferred to be MSEE with minimum of 3+ years, in IP level DV. More experience will be considered as senior engineer or lead.

The candidate should have good understanding on IP/ASIC/SOC design flow and should have:
0. Familiar with one of major verification languages: UVM, C, C++, SystemVerilog, Verilog
1. Good knowledge of design verification methodology, such as UVM or OVM and coverage driven verification methodology
2. Many experiences with simulation model creation and the testbench build
3. Strong RTL coding with Verilog and familiar with front-end design flow
4. Background in one of the area below will be a strong plus:
a. Strong C/C++ software development experiences for ARM based SoC system
b. Video, display, GPU, DDR, PCIe, USB etc..
5. Be familiar with scripting language, such as Perl, C shell, Makefile.

工作职责
The verification tasks include block level, chip level verification, test plan creation, scripting, coverage, regression run etc..