工作职责:
1. Take charge of complex peripheral IP integration in a SoC design, such like USB/PCIE/DDR.
2. Take charge of composing simple IPs according to a design spec.
3. Manage FPGA project for FPGA engineers.
4. Do IP QA for owned IPs, understand the clock, reset and all other interfaces with the whole SoC.
5. Write c code based test cases for owned IPs
6. Run RTL and post simulation and analyze logs/reports for owned IPs
7. Write sdc for owned IPs, and analysis timing reports
8. Write technical documents for all the work above
任职资格:
1.CS or EE MS/BS
2.4+ years of relevant experiences
3. Verilog, C language
4. USB/PCIE/DDR technical key points
5. AXI, AHB, APB bus protocol
6. TCL for syn
7. Perl/Python script