工作职责:
1. Take charge of core IP integration in a SoC design, such like MCU/Cache/Busmatrix.
2. Take charge of composing slightly complex IPs according to a design spec.
3. Help with SoC top clock, reset, power, bus architecture design. Take charge of composing and maintaining SoC top.
4. Manage complex FPGA project for FPGA engineers.
5. Manage the synthesis environment, exchange data with the BE group for syn. engineers.
6. Maintain the simulation environment of a project. Combine the c code compile environment for MCU cores.
7. Do IP QA and write c code based test cases for owned IPs, and run RTL/post simulation, analyze results.
8. Write sdc for owned IPs. Write and maintain the chip level sdc for both synthesis and STA.
9. Write upf and do upf check.
10. Write technical documents for all the work above
11. Evaluation of hardware elements according to ISO26262
任职资格:
1.CS or EE MS/BS
2.6+ years of relevant experiences
3. Verilog, C language
4. SoC architecture key points
5. low power design skills
6. AXI, AHB, APB bus protocol
7. TCL for syn
8. Perl/Python script
9. ISO26262