工作职责:
1. Responsible for the development and support of customer based design form netlist to GDS tape out;
2. Responsible for VLSI chip floor plan;
3. Responsible for CTS, Power plan, Placement & Routing, SPF extraction, timing closure and power analysis;
4. Responsible for whole chip DRC/LVS, and GDS tape out.
任职资格:
1.M.S. or B.S. degree in EE or equivalent
2.6+ years of experience and minimum of BS in EE or equivalent; MS is a plus
3. Experience on whole chip physical implementation.
4. Scripting expertise (Perl, Tcl, or Python) a strong plus;
5. Actual chip tapeout experience on advance technology node (28nm or below) a strong plus.
6. Self-motivated, good communication skill and team work spirit.
7. ISO26262

*公司坚持平等原则，公平公正对待不同背景的员工，包含但不限于国籍、性别、宗教信仰、文化背景等方面，提供平等发展机会，构建多元化人才体系