DESCRIPTION:
- Lead the team on all aspects of physical design on projects


- Participate customer projects evaluation/implementation


- Understand customer needs, dig out potential issues and propose possible solutions to customers


- Contribute to flow setup, development and improvement


- Coordinate DFT implementation with physical design work


- Coordinate and control the physical design work from RTL to GDSII, troubleshooting and control the progress for timely successful tape-out


MINIMUM QUALIFICATIONS:


- MS in Electrical Engineering or equivalent practical experience


- Expert user of EDA tools, such as Synopsys (DC/PT/ICC2), Cadence (GENUS/INNOVUS/TEMPUS) and Mentor (Calibre), etc.


- Experience in Clock/Power Distribution, P&R, Timing closure, RC Extraction, and verification on 40nm, or 28nm technology


- Effective skill with scripting languages, such as Perl, TCL and Makefile scripts
- 5+ years of experience in above areas


PREFERRED QUALIFICATIONS:


- Experience in 20nm/16nm/7nm FinFET or FDSOI technology


- Experience in low power design Implementation including UPF/CPF, multi-voltage domains and power gating.


- Understanding of circuit design, and package design


- Knowledge of various complicated IP usage


- Knowledge of DFT design and DFT architect control


岗位职责描述：
● 参与客户项目前期的评估工作
● 了解客户需求和挖掘潜在问题并为客户提出可能的解决方案
● 带领物理团队进行大型芯片rtl2gds的设计工作
● 协调物理设计团队实现DFT方案和要求




最低要求：
● 电气工程硕士或同等实践经验
● 对Synopsys（DC / PT / ICC2），Cadence（GENUS / INNOVUS / TEMPUS）和Mentor（Calibre）等主流后端开发工具有丰富的使用经验。
● 在复杂芯片布局、时钟/电源分配和sta等方面有较多经验
● 熟练掌握脚本语言（例如Perl，TCL和Makefile脚本）
● 在上述领域有5年以上的经验




优先资格：
● 具有20nm / 16nm / 7nm FinFET或FDSOI技术经验
● 熟悉低功耗设计方法学并有相关设计经验
● 熟悉电路设计和封装设计
● 了解各种复杂IP在物理设计上的用法
● 熟悉DFT设计和DFT架构方面的知识






本职位可在以下两个工作地点上班：


无锡：无锡市滨湖区无锡市滨湖区建筑西路777号A1栋17楼


上海：上海市徐汇区宜山路900号A座1601室