1.Provide high-quality RTL implementation, including assertions writing. Formal tools and static checkers will be used to guarantee RTL quality.
2.Design of state machines, data paths, arbitration and clock domain crossing.
3.Block level synthesis, formal verification, timing constraints/STA.
4.Support design verification team to insure bug-free first silicon .
5.Support generation of various test vectors for block and full chip level simulations.
6.Support physical design teams to insure correct I/O timing definition and perform robust verification of timing parameters.