LPDDR PHY ：
1) 5 years or more of work experience (exceptionally outstanding candidates may have the flexibility in experience requirements).
2) Proficiency in one or more of the following circuit designs:LPDDR2/3/4X/5, PSRAM, eMMC, D-PHY.
3) Basic understanding of LPDDR-related protocols. Capable of independently completing the design and simulation of PHY-related circuits.
4) Ability to assist AE in debugging work during mass production

Phase-Locked Loop ：
1) Five years of work experience or more (outstanding candidates may have flexibility in experience requirements).
2) Proficiency in theoretical analysis of phase noise and jitter,familiarity with PLL design, expertise in both ring-OSC and LC-tank types of VCO, mastery of the entire process of PLL design, optimizing area and power consumption under certain noise specifications. Proficient in using MATLAB and modeling with MATLAB.
3) Responsible for the design and simulation of high-speed SerDes/SOC system PLLs

central analog ：LPDDR PHY 相关方向（源同步接口电路相关）
1)工作5年及以上（特别优秀的同学可以放宽年限要求）。
2) 熟悉lpddr234 / lpddr4x / lpddr5 /PSRAM /
emmc/ C-PHY/D-PHY 电路中的一种或者多种。
2) 对于LPDDR 相关协议有基本的了解。可以独立完成PHY 相关电路的设计和仿真。
3）能够协助AE 完成部分量产上的debug
工作。

central analog ： PLL时钟方向
1） 工作五年以及以上，（特别优秀的同学可以放宽年限要求）。
2） 熟悉phase noise和jitter等理论分析, 熟悉PLL的设计，熟悉ring-OSC和LC-tank 两种类型的VCO ，精通PLL设计的整个流程，在一定噪声指标下优化面积和功耗。
能熟悉使用matlab，使用matlab进行建模
3) 负责高速serdes /SOC 系统 PLL 的设计与仿真。