主要职责：
1.Design and develop high-speed ip for SerDes systems (dp/edp,dphy,cphy, aphy ,etc.) .
2.Farmilar with DP/EDP controller and PHY , Farmilar with video process better .
3.Perform RTL design, simulation, and FPGA validation.
4.Work with cross-functional teams (Application/Ananlog/System/Fusa, etc.) to define specs .
5.Document design processes, simulations, and test plans for reviews/IP handoff.

岗位要求：
1.Education:Bachelor's/Master's in Electrical Engineering or related field ( 3–10 years'experience preferred).
Core Skills:
a.Strong fundamentals in digital circuit design (Experience IP deisgn with SERDES or VESA dp/edp or Video process.
Interface Knowledge:
a.Familar with Display timing adjustment (DP/EDP/HDMI, etc.).
b.Exposure to MIPI/VESA protocols(DP/EDP/DSC/DPHY/CPHY, etc.) is a plus.
2.Soft Skills:
a.Strong problem-solving, teamwork, communication and clear documentation abilities.
b.Adaptability in fast-paced R&D environments.
3.Bonus Qualifications
a.Quality/Process Compliance:
i.Knowledge of ISO 9001 or IATF 16949quality management systems.
ii.Awareness of automotive/industrial functional safety (FuSa) standards (ISO 26262, IEC 61508).
b.System Modeling:MATLAB/Python for behavioral analysis.
c.Tape-out experience or published SerDes/video design work.